The present invention relates to a synchronous semiconductor memory device, and more particularly, to a synchronous semiconductor memory device that sets a plurality of column address strobe (CAS) latencies.
A synchronous semiconductor memory device (synchronous SDRAM, hereafter referred to as SDRAM) reads cell information in correspondence with a predetermined CAS latency.
FIG. 1 is a schematic partial block circuit diagram of a prior art SDRAM 200. The SDRAM 200 receives a read command in synchronism with an external clock signal. Based on the read command, the SDRAM 200 reads cell information (data) from a memory cell to a bit line. The read data is output from external pins via a sense amplifier (not shown), a column gate (not shown), a data bus (not shown), a read amplifier 1, and an output circuit 2.
The SDRAM 200 further includes a register block 3 located between the read amplifier 1 and the output circuit 2. The register block 3 latches data based on an external clock signal and provides the latched data to the output circuit 2 in correspondence with the predetermined CAS latency.
The register block 3 includes three registers 11, 12, 13, which are connected in parallel, and a register 14. The input terminal of the register 11 is connected to a transfer gate Ti1, and the output terminal of the register 11 is connected to a transfer gate To1. The input terminal of the register 12 is connected to a transfer gate Ti2, and the output terminal of the register 12 is connected to a transfer gate To2. The input terminal of the register 13 is connected to a transfer gate Ti3, and the output terminal of the register 13 is connected to a transfer gate To3. The register 14 is connected in series to the parallel-connected registers 11-13.
The transfer gates Ti1, Ti2, Ti3, To1, To2, To3 are respectively activated and deactivated by control signals in1, in2, in3, out1, out2, out3, which are generated in correspondence with the CAS latency. The registers 11-14 latch a read data signal S1, which is provided from the read amplifier 1 to the register block 3. The latched data is output to external pins via the output circuit 2 at a timing based on the external clock signal CLK.
FIG. 2 is a combined timing and waveform chart illustrating the operation of the SDRAM 200 when the CAS latency is set at a value of "3".
If the SDRAM 200 receives a read command when the external clock signal CLK goes high (time t1 ), the read amplifier 1 amplifies the data read from a memory cell and provides the amplified read data signal S1 to the register block 3. This first activates the transfer gate Ti1 of the register block 3 based on the control signal in1 and latches the read data S1 with the register 11. Based on the control signal out1, the transfer gate To1 is then activated and the read data signal S1 is transferred to the register 14. Afterward, the output data becomes effective based on the external clock signal CLK (time t4 ).
The parallel connection of the three registers 11-13 divides a read circuit into a plurality of operational stages. Thus, the read circuit is controlled as a parallel-connected pipeline. In response to high operational frequencies, the SDRAM 200 receives continuous commands and easily performs data read control.
When the CAS latency is set at the value of "1", the transfer gates Ti1, To1 are constantly activated. Thus, at time t2, the read data signal S1 is provided to the output circuit 2 via the registers 11, 14 and the output data becomes effective.
Further, if the CAS latency is set at the value of "1", the output data must become effective when the clock signal CLK goes high in the cycle following the cycle during which the read command is received (time t2 ). For example, if data is immediately read from the read command in the same manner as random access, the CAS latency is set at "1".
However, the register block 3, which is arranged along the output route of the read data signal S1 to perform pipeline control, prolongs access time. The access time refers to the time from when the SDRAM 200 receives the read command to when the read data is output.
As shown in FIG. 3, when the CAS latency is set at the value of "1", the necessary access time is shorter in comparison to when the CAS latency is set at the values of "2" or "3". Thus, the margin in operational time of internal circuits is small, and the access time may be insufficient.